The present invention relates generally to methods and apparatus for fast addition. More particularly, the present invention relates to quickly generating a plurality of counts from a base count.
In microprocessors, it can be efficient to process a subset of instructions out of their original order. However, it is often necessary to actually execute subsets of the instructions in their original order. For instance, a first instruction may generate a result that is to be used as an argument of a second instruction. If the second instruction were to be executed prior to the first instruction, the second instruction would generate an incorrect result. Therefore, it would be useful to generate identifiers for the instructions that indicate a particular order in which to execute the instructions. However, such identifiers would need to be generated extremely quickly given the clock speed of typical microprocessors.
What is needed are techniques for quickly generating identifiers that can be used to execute instruction in a correct order.